AHB Lite Vs AHB
AHB Lite is a reduced version of AHB protocol. AHB Lite essentially means that there is only 1 master.
This in turn means
1. No Arbitration
2. No HBUSREQ signal, no HGRANT signal
3. No HSEL Signal
4. No Split or Retry response type -> HRESP can only be 1 bit
5. No Early Bus Termination.

How to connect a full AHB Master to AHB Lite Slave
1. Leave the HBUSREQ open
2. Tie the HGRANT to '1'

How to connect a AHBLite Master to full AHB Slave
1. Feedback the HREADY_out from the Slave back into the HREADY_In at slave (A slave will have hready as input and as output)
     But also connect the HREADY_out from Slave to the Master.

2. Tie the HSEL '1' at the Slave.

Where is AHB Lite Used:
One of the main applications of AHB lite is in Multilayered AHB designs.
Cortex-M processors have AHB lite interfaces ONLY.

How AHB Lite works: A typical example
The full AHB version has HBUSREQ & HBUSGRANT signals. Typically a master will request the shared bus using HBUSREQ,
and unless the bus is granted to it, it wont start transactions.
This means that only one Master+Slave pair can communicate at a given time.
However, if a Multilayered AHB bus is used, it allows several Master+Slave pairs communicate simultaneously, giving a huge
boost to system performance.
In Multilayered designs, all masters have the bus 'granted' to them all the time. They can start transactions whenever they like.
However if the Slave say S2, is being addressed to by the Master say M10, and the Slave S2 is already busy, the Master M10, will have
its 'address phase' registered in the bus/interconnect, and HREADY towards the master will be asserted 'low'. The master M10 will wait till S2 is free.
Above example shows how there is no need for HBUSREQ and HBUSGRANT. HBUSREQ/HBUSGRANT will also increase system latency
as it will just add at least 1 more extra clock cycle before a master could start a transaction.

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KeyWords: AHB Lite Vs AHB, connect AHBLite to full AHB