AXI Vs AHB OR AHB Vs AXI Difference between AXI and AHB
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This techerature compares AMBA AHB protocol to AMBA AXI protocol.
AHB : Advanced High performance Bus
AXI : Advanced Xtensible Bus:

AHB is ARM's most popular protocol, which was invented in an era, where the computing power of the Integrated Circuits were very primitive as compared to what we have now (2019)
As the computing demands rise, AHB started to fall short in meeting the demands of the system which were ever hungry for more bandwidths. AXI was then invented. One of the major problems with the AHB protocol is its inability to support what are called 'outstanding' transactions. An outstanding transaction is simply the one, which has been issued but its response is awaited. Yes, mostly it is related to 'read' transactions, as the 'write' transactions can live without a response.
Though AHB does support 'split' transactions which one may argue that its what an outstanding transaction support in AHB is, but it never took off, and neither did it served the purpose of 'outstanding' transactions.
Issuing several outstanding transactions, without receiving the response helps in increasing throughput as can be seen from the diagram and related text below:
But let us consider the objective differences between the 2.
The following table highlights the differences between the 2, however this is by no means an exhaustive list of differences.
 

AHB
 AXI
Has 1 address channel, 1 read data channel, 1 write data  channel                                                                                                                                                                                                                                       
Has 1 read address channel, 1 write address channel, 1 read data channel, 1 write data channel. 1 write response channel That is altogether it has 5 parallel channels. (The first AXI version had just 1 address channel)
Does not support outstanding reads, though with writes, the master can issue multiple write transactions, marking them as 'bufferable' so that if the interconnect is able to respond immediately, the master would consider the transaction over, and would issue subsequent transactions immediately in the next clock cycle.
 Has native support for multiple outstanding transactions.
No concept of channels.
 AXI supports transaction IDs. The user may issue multiple outstanding transactions per transaction ID. A transaction ID can relate to a data stream. Hence by issuing multiple outstanding transactions per ID, AXI gives the user the power to have 'channels' of data.
It does not support pipeline registers in its path, if user is not able to meet timing requirements.
User can insert a pipeline register anywhere in the path of any of the 5 channels, which helps in timing closure and help achieve higher operating frequency.
Due to its in-ability to support pipeline registers insertion, AHB limits the max freq for the design. This can hit hard, on the SoCs which are big, and may have long distances for the datapath to cover.
 AXI enables higher frequency of operation due to its support for 'pipe-line' register insertion.
Number of wires are less
 Since AXI has 5 parallel channels running, it has a lot of more wires, which may cause congestion in layout.
Limited Throughput.
 Extremely high Throughput
No inherent support for side-band signals
 AXI 4 supports AxUSER bits, i.e. it has support for side-band signals.
No QoS Support
 AXI 4 supports QoS
Burst Lengths are fixed i.e 1, 2, 6, 16 except for INCR types, where it can be anything as long as it does not cross 4K boundary.
 Burst lengths can be anything, from 1-16 for AXI3, and 1-256 for AXI4.
The 'INCR' type burst can have any length, but there is no information available at the start of the burst, how long it might be.
 The length of the burst is always known right at the start. This feature is supported by using AxLEN bits.
Strongly Ordered: Since there is at a time only 1 active transactions, the transactions are strongly ordered in the sense, that the responses received to any transaction(s) follow the same sequence as the transactions were issued.
 Since it supports multiple outstanding transactions, i.e. many transaction is issued at a time, the responses to different transactions can arrive out of order. However the responses to each 'channel' will still be ordered, i.e to say responses with same ID must return in order
Low power dissipation
 Higher power dissipation.
Write Strobes are not supported.
 Write Strobes Are supported
Locked Transfers are supported
 AXI3 supports Locked Transfers, AXI4 does not support Locked Transfers.
Exclusive transfers are Not Supported
 Exclusive transfers are supported.



AXI vs AHB : How-come AXI offers higher performance and throughput than AHB.
It can be observed from the above table it has been mentioned that AXI offers high throughput, i.e high performance. However its rather uncommon to know the actual reasons
and circumstances in which AXI would offer performance boost.

The following section attempts to explain the actual reasons and the circumstances
in which AXI offers performance boost.

There are 2 basic reasons why AXI may be faster:

1. Simplex Vs Duplex Transfers
AXI has completely independent channels for read/write, which enables full duplex mode of data transportation. That is to say read and writes can take place simultaneously, giving 2x boost over AHB in any circumstances. However this will ONLY be possible when the slave is able to process 1 read and 1 write operation simultaneously in 1 clock cycle. Which in many cases will be possible, e.g. if the slave is a dual port SRAM which can process 1 read and 1 write transaction simultaneously. Also in this example we are considering 1 Master and 1 Slave. But in case of multiple slaves, the master can send read transaction to 1 slave and write to other slave, even if the slave(s) cannot handle more than 1 transactions in single clock cycle.

To make more clarity, in a system where there is only 1 master and only 1 slave, the slave is unable to process read and write in 1 single clock cycle simultaneously and both master and slave are in single synchronous clock domain with no clock delay between the master and the slave there wont be any difference in performance between AXI and AHB. The AXI will only consume more power and area.
2. When there are clock cycle delays between a Master and a responding slave.
-This is usually when the Master clock and slave clock is Async, and a there is a clock domain crossing bridge.

It can be  observed in the diagram shown below, that that as the number of OTs (outstanding transaction) increase in AXI, the efficiency increases. It can also be observed that with 1 OT, again, the performance will be comparable, if we are doing only reads or only writes.
In AXI case, since the system is able to issue outstanding transactions (OT), i.e. able to issue addresses without waiting for data to return, there is only a initial delay, and then the continuous flow of data follows.
In AHB this is not possible. The AHB cannot issue another transaction, without first receiving the response to its only transaction, which it can issue at a time.

 

It is to be noted again, that if there are no clock delays between a master and a slave, and if we assume only 1 master and 1 slave in the system, then again the AXI performance will be equal to AHB performance, if we are doing only reads or only writes.







Conclusion:
The differences in the above table highlight, that AHB may be used in a completely synchronous system which are contained in small silicon areas, e.g for small SoCs i.e IoT SoCs, Audio SoCs. It may also do well in synchronous subsystem within a larger SoC. AHB is generally used in systems which do not have high throughput demands, or in the systems where the frequency of operation is relatively lower i.e < 150 MHz.
However if the SoC is large, has multiple clock domains, or if a subsystem is large and has multiple clock domains and the demand for throughput and bandwidths are high, the frequency of clock are higher e.g. 200+ MHz, then AXI is the way to go.


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