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Section 2
This Section describes the ARM's AHB
Multilayered Bus Matrix RTL
generation:
This component is a multilayered AHB bus which is used to connect
the processor to the memories. Actually the bus matrix is connected
to AHB2SRAM designs, before the memories, and the memories are then
connected to AHB2SRAM designs.
The AHB2SRAM designs convert the AHB protocol signals to SRAM
signals.
The ARM's Multilayered Bus Matrix IP is present in the following
directory: (This directory would have been created by the user
following the download of the ARM Design Start Eval Cortex-M3
processor Kit from ARM's website, as described
in the previous section).
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix
This directory has 3 following directories:
bin
verilog
xml
The RTL
generation is done by providing the specification for the matrix
using a configuration xml file. This configuration xml file must be
present in the 'xml' directory. By default ARM provides some example
configuration files The
configuration xml file for this tutorial has been prepared for the
user to analyze it.
The specification of the matrix includes the following:
- The number and names of Bus Matrix AHB Slave ports (which will
connect to the system Master Ports)
- The number and names of Bus Matrix AHB Master ports (which
will connect to system Slave Ports)
- The address range(s) of the Bus Matrix AHB Master Ports.
- The Connectivity definition of the Bus Matrix Slave ports to
Bus Matrix Master ports.
- The Arbitration scheme used.
The XML config file is briefly described in the figure below:
Once the configuration is specified, the script 'BuildBusMatrix.pl'
is used to generate the Bus Matrix RTL.
Full command syntax is also provided. Keep reading.
The 'cmsdk_ahb_busmatrix' component supports up-to 15 Masters
and 15 Slave.
In this tutorial this IP is configured to use 5 Slave Ports (to
which the system masters would connect to) and 4 Master Ports (to
which the system Slaves will connect to). Remember
as per the AHB protocol, the AHB protocol signals are asymmetric,
i.e. a Master connects to a Slave and a Slave connects to a
Master. Throughout this tutorial/course this has to be kept in
mind.
The following figure provides the specification of the Bus Matrix we
intend to built RTL for:
The figure above is quite self-explanatory:
- The System Master M0 connects to the 'Bus Matrix Slave Port
S0' on the Bus matrix and has connections to the System Slaves
S0 and S1
- The System Master M1 connects to the 'Bus Matrix Slave Port
S1' on the Bus matrix and has connections to the System Slaves
S0 and S1
- The System Master M3 connects to the 'Bus Matrix Slave Port
S3' on the Bus matrix and has connections to the System Slaves
S3 and S2
- The System Master M4 connects to the 'Bus Matrix Slave Port
S4' on the Bus matrix and has connections to the System Slaves
S0, S1 and S2
- The System Master M5 connects to the 'Bus Matrix Slave Port
S5' on the Bus matrix and has connections to the System Slaves
S0, S1 and S3
While the above describes the connectivity, the following describes
the System Slave address regions.
- System Slave S0
-> Has address region 0x0000_00000 -> 0x0000_FFFF (64K)
- System Slave S1
-> Has address region 0x0001_00000 -> 0x1000_FFFF (64K)
- System Slave S3
-> Has address region 0x2000_00000 -> 0x2001_FFFF (128K)
- System Slave S2
-> Has address region 0x4000_00000 -> 0x4000_FFFF (64K)
Yes, there is no System Master M2 (and corresponding S2 port on Bus
Matrix) and the order of System Slaves isn't in increasing order
(going from left to right, S3 comes before S2), but this doesn't
matter, and there isn't any technical reason behind this naming.
Things to Note:
- The 'connectivity' of the bus matrix is what is called 'sparse
connectivity'. This means every System Master is not connected
to every System Slave. If every system Master will be able to
connect to every System Slave, then the connectivity is
described as 'full connectivity'
- There is a default slave which is not shown above. The default
slave will respond if any System master attempts to send a
transaction to non-existing address, or it attempts to a System
Master which it is not configured to be connected to.
To configure the ARM's bus matrix to the above specification, the
'xml' spec file, described above is needed.
An example 'xml' file is provided in the following directory by ARM:
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix
We
take the example xml configuration file and configure it to the
above spec to get this.
When you click on line above, you will see the contents of an xml
file.
Copy+Paste it into a file and name it 'cortexm3_soc.xml'.
Note: Remember to name the file as '.xml', when you click on above
link the file is shown as .txt.
Save the above as 'cortexm3_soc.xml' in the 'xml' directory.
Make sure that you have the directory called
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix/verilog/built
If not then make it
mkdir AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix/verilog/built
Now issue the following command from the directory:
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix
./bin/BuildBusMatrix.pl -xmldir xml -cfg cortexm3_soc.xml -over
This may give you the following error:
"Unescaped
left brace in regex is deprecated, passed through in regex; marked
by <-- HERE in m/}{ <-- HERE ([a-z0-9\.\-\_]+)\[1\]$/ at
bin/lib/xmlparser.pm line 852."
If (and only if) you get this error, then open the file
'bin/lib/xmlparser.pm' and edit line number 852 as shown
below:
if ( =~ s/}{([a-z0-9\.\-\_]+)\[1\]$// ) { = ; }
if ( =~ s/\}\{([a-z0-9\.\-\_]+)\[1\]$// ) { = ; }
All you have to do is, put a backslash '\' before the '}' and '{'
characters as shown above.
Save the file and try the build command again.
./bin/BuildBusMatrix.pl -xmldir xml -cfg cortexm3_soc.xml -over
This will generate the Bus-Matrix RTL
for the above spec.
The RTL will be present tin the following directory:
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_busmatrix/verilog/built
Copy the following RTL
files from the above directory to the directory:
'asic_design/xilinx/cortexm3_soc/cm3_matrix/rtl'
You may have to create this directory:
cm3_in.v
cm3_matrix.v
cm3_matrix_default_slave.v
cm3_matrix_lite.v
cm3_outM0.v
cm3_outM1.v
cm3_outM2.v
cm3_outM3.v
cmsdk_MyArbiterNameM0.v
cmsdk_MyArbiterNameM1.v
cmsdk_MyArbiterNameM2.v
cmsdk_MyArbiterNameM3.v
cmsdk_MyDecoderNameS0.v
cmsdk_MyDecoderNameS1.v
cmsdk_MyDecoderNameS3.v
cmsdk_MyDecoderNameS4.v
cmsdk_MyDecoderNameS5.v
Note: The file 'cm3_matrix_lite.v' contains the TOP
level for the Bus Matrix.
All the components needed to create the first SoC RTL
are now ready to be used.
Next these components will be 'connected' together to build the
Stage 1 SoC RTL.
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