This web course is about Designing a System on Chip using ARM's
Cortex-M3 processor.
All the material needed for this tutorial i.e. Tools & RTL
Source Code/C&Assembly Source Code is either available on this
web site or can be obtained free of charge from various companies.
See the 'Tutorial Resources' section below to get these.
This SoC design Tutorial will be posted on this web site in Stages.
The First Stage of this course is now complete and is available. The
idea is to learn how to design a System on Chip from scratch. The
First Stage, i.e. Stage 1 is about building a very simplistic SoC
with a processor and 2 memories. With each stage, more components
will be added to make the SoC more capable, and feature rich.
The processor chosen for the SoC is ARM's Cortex-M3 processor. This
is because the RTL
for this processor is now available free of charge from ARM's web
site to everyone, along with the RTL of
other critical components that are used in this web-course.Again
follow the links under 'Tutorial Resources' to get it.
The course wont go into the details of the processor itself, as
there are plenty of web-sites which will enable the user/reader to
get a basic idea of this processor. The course rather focuses on its
main objective i.e. SoC design. Nevertheless,
an objective integration guide to the Cortex-M3 processor can be
found here, which explains the I/Os of this processor.
It is a very practical/hands-on course, where the user will perform
the following:
- Build the RTL
for their own SoC
- Write basic small software in C & Assembly
- Compile the Software, and produce a binary/hex executable.
- Perform a RTL
level simulation of the SoC, with the binary/hex code running.
The binary software code will be read by verilog memory model.
Just imagine the power of this Tutorial/Web Course: The user starts
from scratch with 0 knowledge, and ends up in a day having
designed/Built/Simulated their own System-on-Chip, with their own
software program running on the SoC.
These kind of tutorials or as they call it 'courses' are not
available for free anywhere else on this planet. A class-room course
for this kind of learning can easily cost north of $2500.
The tutorial does not use difficult words, any jargon (that is not
explained) its very simple to understand and follow.
Ever heard of Software/Hardware co-simulation? Yes, after finishing
off this tutorial the user will know exactly what it is.
And before we start, if you don't have access to Linux machine, you
may have to install Linux on Windows,
for one of the steps of the tutorial, that is 'Bus Matrix
Generation'
Again see the 'Tutorial Resource' section on how to do that.
Target Audience:
ASIC design Engineers, System on Chip Design Engineers, Logic Design
Engineers, Embedded Software Engineers, Students, Professionals.
Tutorial Resources:
The Tutorial
A Basic SoC will have a processor, a memory, and some
software loaded on the memory.
The following figure provides the Architecture level diagram of the
First SoC that this tutorial builds.
As shown the main processor is ARM Cortex-M3 processor.
The processor is connected to ARM
Multilayered Bus Matrix.
The ARM Multilayered Bus Matrix is connected to 2 memories.
The ARM Cortex-M3 processor has following 3 AHB-Lite
Interfaces to connect to the system.
1. ICODE Bus
2. DCODE Bus
3. System Bus.
The 'Bus-Matrix' in the above figure is a multi-layered ARM provided
AHB Lite Bus Matrix.
This component is also provided by ARM free of charge with the Cortex-M3
Design Start Eval Kit.
In the Tutorial RTL,
the Bus Matrix is configured to use more ports than shown in the
above diagram. But only the ports which are shown above are used,
the rest are tied to appropriate values so that they remain dormant.
Step 1: Setup RTL
file(s).
1.1a Create a directory called asic_design.
1.1b Inside 'asic_design' create a directory called 'xilinx'.
1.1c Inside 'xilinx' directory create a directory called
'cortexm3_soc'.
1.1d Inside 'cortexm3_soc' create the following directories:
'cm3_matrix', 'CORTEXM3INTEGRATION', 'cmsdk_ahb_to_sram', 'top' and
'cmsdk_fpga_sram'
1.1e. Inside the following directories create directory called 'rtl'
- cm3_matrix/rtl
- CORTEXM3INTEGRATION/rtl
-
cmsdk_ahb_to_sram/rtl
- top/rtl
1.1f Inside cmsdk_fpga_sram create directory called 'verilog'
cmsdk_fpga_sram/verilog
1.2: Setup ARM RTL.
This step defines what RTL
source files you need for this tutorial and where in the ARM's
standard Cortex-M3 Kit they are located. If for some reason you have
not been able to download the Cortex-M3 from ARM, you can download the
source code for this tutorial, and that will give you all the
required files.
Download ARM Cortex-M3
Design Start Eval Kit and place the downloaded
AT421-MN-80001-r0p0-02rel0.tar.tz file inside your
'asic_design' directory.
Ungzip and Untar the above
file
gzip -d AT421-MN-80001-r0p0-02rel0.tar.tz
-> The above step will
create a .tar file 'AT421-MN-80001-r0p0-02rel0.tar'
tar -xvf
AT421-MN-80001-r0p0-02rel0.tar
-> The above step will
create the directory AT421-MN-80001-r0p0-02rel0, and
populate it with the required contents.
- Copy the file following
2 files in your 'asic_design/xilinx/cortexm3_soc/CORTEXM3INTEGRATION/rtl'
directory.
AT421-MN-80001-r0p0-02rel0/m3designstart/logical/cortexm3integration_ds_obs/verilog/cortexm3ds_logic.v
AT421-MN-80001-r0p0-02rel0/m3designstart/logical/cortexm3integration_ds_obs/verilog/CORTEXM3INTEGRATIONDS.v
The above 2 files are
the Cortex-M3 processor's source code RTL.
- Copy the file following
file in your 'asic_design/xilinx/cortexm3_soc/cmsdk_ahb_to_sram/rtl'
directory.
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
The above file is the
source code RTL
for the AHB2SRAM bridge. This design converts the AHB protocol
signals to a simple SRAM signals.
- Copy the file following
files in your 'asic_design/xilinx/cortexm3_soc/cmsdk_fpga_sram/verilog'
directory
AT421-MN-80001-r0p0-02rel0/cmsdk/logical/cmsdk_fpga_sram/verilog/cmsdk_fpga_sram.v
AT421-MN-80001-r0p0-02rel0/m3designstart/logical/fpga_top/verilog/fpga_options_defs.v
The above 2 files are the source code for the
SRAM.
The above steps makes sure that you have all the RTL
source code files except for the AHB Bus Matrix.
Since the AHB bus matrix RTL
needs to be custom built using configuration file, it is given due
importance and its generation is described in next section in
detail.
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Comments or ask Questions
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(Configure & Build AHB Bus Matrix) =>
Keywords:
Software Hardware Co-Simulation
Hardware Software Co-simulation
SoC design from Scratch using ARM Cortex-M processor.