Its important to first understand
what is TLM or transactional Level Modelling?
The name for sure sounds
intimidating, but the concept is really simple. And this is
what the UVM/OVM
concepts are based upon. if you
already know what is TLM, you may want to skip this section.
Once upon a time, in Silicon Valley,
we used to write testbenches, which used to drive each and
every signal of
the DUT, with the stimulus specified
for each input at each clock cycle.
Now, of course we dont do that.
What we do is, we define what is
called a 'data item'. This is the 'unit' of stimulus which the
UVM/OVM
testbench generates or will generate
upon command or upon request.
So TLM does not generate individual
signals at individual clock cycles, TLM means a method to
generate
a 'data item' and drive the same as
stimulus to the DUT or DUT interface.
Heyyyy... but what is TLM.
Its the way of modelling a testbench
which generates a 'data item' instead of individual stimulus
for each input
on the DUT or a specific interface of
DUT, which is under test is called TLM.
Heyyyyy... but what is a 'data item'.
A Data Item is the smallest Unit
produced by TLM testbench or TLM model. Following is an
example of a data item.
Note: Do not get intimidated by the
syntax, the tutorial will explain the syntax in detail at a
later stage.
`include "ahb_typedefs.v"
class ahb_mtran extends uvm_sequence_item;
rand bit [`AW-1:0] haddr;
rand HTRANS_t htrans;
rand bit hwrite;
rand bit [2:0] hsize;
rand HBURST_t hburst;
rand integer BL;
rand bit [3:0] hprot;
rand bit [`DW-1:0] hwdata;
rand integer b2b_delay; //this is the delay
between 2 consequtive trans issued by a master
rand bit en_b2b_delay; //0 => disable
b2b_delay.,1=> enable b2b_delay
function new (string name = "");
super.new(name);
endfunction: new
endclass: ahb_mtran