-Aviral Mittal
Interface Writing.
As indicated in previous sections, to be able to write a UVM
compliant Testbench we will need
to write some classes, some modules and an interface.
Lets start with the interface.
Interface, as the name sounds is usually an I/O list, which a DUT
uses to interact with outside world.
Interface in UVM is also used to connect the UVM Testbench world
with the Verilog DUT world.
UVM will drive the interface, and this interface will be connected
to the DUT.
That is how UVM and DUT interact with each other.
In this tutorial we are trying to write a UVM compliant VIP which
may be used to drive a AHB Slave port.
I.e. the UVM VIP will mimic an AHB Master.
Interfaces are written in System Verilog, no use of UVM in interface
definition.
So let us first write the interface:
interface
ahb_if();
logic hclk;
logic hresetn;
logic [32-1:0] haddr;
logic [1:0] htrans;
logic hwrite;
logic [2:0] hsize;
logic [2:0] hburst;
logic [3:0] hprot;
logic [32-1:0] hwdata;
logic [32-1:0] hrdata;
logic hready;
logic [1:0] hresp;
endinterface: ahb_if
Save the above as ahb_intf.sv
Its very intuitive, it has signals which an AHB master is expected
to drive/accept.
Notice it also has clk and reset, but this wont be driven by UVM TB.
So now we have an interface which will be driven by UVM TB, and will
connect to a AHB Slave DUT.
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KeyWords: OVM, UVM, SystemVerilog, Constrained Random
Verification, Transaction Level Modelling.