OVM/UVM: A Practical
Tutorial Using System Verilog
-Aviral Mittal
Transaction Class.
Now we will write a 'Transaction Class' which will have fields
corresponding to the fields of the 'Interface'.
Here we will also define some verilog typedefs, which we will use in
'Transaction class'
Save the following as ahb_typedefs.v
typedef enum
{SINGLE=0,INCR=1,WRAP4=2,INCR4=3,WRAP8=4,INCR8=5,WRAP16=6,INCR16=7}
HBURST_t;
typedef enum {IDLE=0,BUSY=1,NONSEQ=2,SEQ=3} HTRANS_t;
`define AW 32
`define DW 32
function [4:0] bl;
input HBURST_t hburst;
begin
if(hburst==0) bl = 1;
if(hburst==1) bl = 0;
if(hburst==2) bl = 4;
if(hburst==3) bl = 4;
if(hburst==4) bl = 8;
if(hburst==5) bl = 8;
if(hburst==6) bl = 16;
if(hburst==7) bl = 16;
end
endfunction
Save the following as ahb_mtran.svh
`include
"ahb_typedefs.v"
class ahb_mtran extends uvm_sequence_item;
rand bit [`AW-1:0] haddr;
rand HTRANS_t htrans;
rand bit hwrite;
rand bit [2:0] hsize;
rand HBURST_t hburst;
rand integer BL;
rand bit [3:0] hprot;
rand bit [`DW-1:0] hwdata;
rand integer b2b_delay; //this is the delay between 2
consecutive trans issued by a master
rand bit en_b2b_delay; //0 => disable b2b_delay.,1=>
enable b2b_delay
`uvm_object_utils_begin(ahb_mtran)
`uvm_field_enum (HTRANS_t, htrans,
UVM_ALL_ON)
`uvm_field_enum (HBURST_t, hburst,
UVM_ALL_ON)
`uvm_field_int
(haddr,
UVM_ALL_ON + UVM_HEX)
`uvm_field_int
(BL,
UVM_ALL_ON + UVM_DEC)
`uvm_field_int
(b2b_delay,
UVM_ALL_ON + UVM_DEC)
`uvm_field_int
(en_b2b_delay,
UVM_ALL_ON + UVM_DEC)
`uvm_field_int
(hwrite,
UVM_ALL_ON + UVM_BIN)
`uvm_object_utils_end
constraint ahb_bl {BL inside {[1:16]};}
constraint b2b_delay_c {b2b_delay inside {[0:3]};}
function new (string name = "");
super.new(name);
endfunction: new
endclass:
ahb_mtran
Save the above as ahb_mtran.svh
The first line is very simple, its an include statement for the file
ahb_typedefs.v, which is also shown above.
The second line is the definition of the class. 'ahb_mtran' is a
user defined name,
it 'extends' the basic UVM class uvm_sequence_item. Every
transaction class is directly or indirectly
have to be derived from (extended from) the uvm base class
'uvm_sequence_item'
This class can be seen as a user defined data type.
Next are the fields present in this class. Notice the keyword 'rand'
in front of the fields.
This means that these fields will be populated with random values,
adhering to some 'constraints'
whenever an instance of this data type is created.
(We will see how to create instances in testbench later).
Now constraints can be user defined, or it can originate from the
data type of the field.
For example the field 'hsize' is [2:0], that automatically
constrains it to a value between
3'b000 and 3'b111. So in this case the constraint for 'hsize'
originate from the data type of the field.
Next we see macro 'uvm_object_utils begin & end
This is just a formality which 'registers' this class in the UVM
factory.
In short, for every class, you will have to write these statements.
Within `uvm_object_utils begin and end, we see the following
`uvm_field_enum or `uvm_field_int etc.
These are additional statements, which help in printing the values
of the fields of this class, whenever needed.
These statements also define the format in which each field will be
printed.
For example, the field haddr will be printed in Hex (UVM_HEX),
the field BL will be printed in Decimal (UVM_DEC),
We will see how to print these later.
Then you will notice some user defined 'constraints'.
For example, a constraint named 'ahb_bl' is defined. This constrains
the field 'BL' to take a
value between 1 and 16.
Then you will see the function 'new'.
This has to be written in all class definitions.
Notice that this class is derived from 'uvm_sequence_item'. This is
hence a 'data item' and
it has no place in UVM component hierarchy. (Refer to the UVM
class hierarchy diagram on this page)
This completes this Transaction Class Chapter.
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Next
-> (Driver Class)
KeyWords: OVM, UVM, SystemVerilog, Constrained Random
Verification, Transaction Level Modelling.