OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal


Sequence Class.

 Again a Sequence is a 'data item' its not a component.
It usually has a 'body' method/task, which is where we can define a 'sequence' of a test flow.

This means a sequence (chain of events) in which we want the transactions to be generated, and passed to the driver.
In the following sequence, a single transaction is generated, randomized, and is sent to the driver.

class ahb_msequence extends uvm_sequence #(ahb_mtran);
  `uvm_object_utils(ahb_msequence)
  rand int itr;
  constraint itr_num {itr inside {[100:200]};}
  rand int b2b_delay;
  rand bit en_b2b_delay;
  constraint b2b_delay_c {b2b_delay inside {[0:5000]};}


  rand int haddr;
  constraint haddr_c {haddr inside {32'h8000_6000,32'h2000_8000};}


  function new (string name = "");
    super.new(name);
  endfunction: new

  task body;
        ahb_mtran tx;
        tx = ahb_mtran::type_id::create("tx");
        start_item(tx); //indicates to the driver that we have a tran ready to go
        //when start_item returns, => driver is ready to receive the item
        //driver is ready to receive the tran.
        assert (tx.randomize());
        tx.b2b_delay = this.b2b_delay;
        tx.haddr = this.haddr;
        tx.en_b2b_delay = this.en_b2b_delay;
        finish_item(tx); //this sends the transaction to the driver
        //start_item,finish_item syncronises with the driver.
  endtask: body

endclass: ahb_msequence

Save the above as ahb_msequence.svh

tx = ahb_mtran::type_id::create("tx"); -> This creates an instance of the transaction type ahb_mtran.
The instance is called 'tx'.

start_item(tx); -> this indicates to the driver, that a transaction is ready.
when start_item returns, the driver is ready to receive the transaction.

assert (tx.randomize()); -> here the transaction tx is randomized.
if for some reason the randomization will fail, then the 'assert' statement will help throw and error for the user to know.

Here we also have the chance to modify the randomly generated fields of the transaction and give them a desired value if the need be.

After modifying the fields (if the need be), we call
finish_item(tx); -> this is when the transaction is actually sent to the driver, via something which is called a 'Sequencer'
Again its all magically done, and we don't have to worry about how.

This is a very elementary sequence, we can have more elaborate sequences, which may call other sequences.
There is also something which is called 'virtual sequences' which we will learn later.
 

This completes this Sequence Class Chapter.


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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.