OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal


Sequencer Class.

A sequencer class is a very standard code, and usually there is no need for a user to modify the standard code.
It can be coded in just 1 line

typedef uvm_sequencer #(ahb_mtran) ahb_msequencer;

Save the above as ahb_msequencer.svh

Technically the job of sequencer is to pipe transactions generated in a sequence to the driver.

Sequence Vs Sequencer
Sequence is just a chain of events, its a data item, it has no place in UVM component hierarchy
While
Sequencer is a component in UVM component hierarchy.

This completes this Sequencer Class Chapter.

<- Previous(Sequence Class)                                                                                Next -> (Agent Class)

KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.