UVM Tutorial Agent Class

OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal

Agent Class.
An agent class is derived from the uvm base class 'uvm_agent'.
An agent by the definition of UVM standard, will instantiate the following:
A Driver
A Sequencer
A Monitor

Note: we wont be using a monitor, so our agent will have driver and sequencer only.

The agent is an entity, which will usually be 1 per DUT interface. That is to say
that one agent will be present in UVM env per DUT interface.

class ahb_magent extends uvm_agent;
`uvm_component_utils(ahb_magent)
//declare pointers to sub components
ahb_msequencer ahb_msequencer_h;
ahb_mdriver ahb_mdriver_h;
virtual ahb_if dut_agent_vi;

//constructor
function new (string name, uvm_component parent);
    super.new(name, parent);
endfunction: new

//build
function void build_phase(uvm_phase phase);
//instantiate subcomponent in build phase and connect them in the connect phase
    ahb_msequencer_h = ahb_msequencer::type_id::create("ahb_msequencer_h",this);
    ahb_mdriver_h    = ahb_mdriver::type_id::create("ahb_mdriver_h",this);
    //ahb_msequencer_h is the instance name, 'this' is the parent
    //so the above instance will be build as children of ahb_magent component
    //type of object can be overriden in the test

    ahb_mdriver_h.dut_vi = dut_agent_vi;
endfunction:build_phase

function void connect_phase(uvm_phase phase);
      ahb_mdriver_h.seq_item_port.connect(ahb_msequencer_h.seq_item_export );
    //seq_item_port is by default present in ahb_mdriver
    //seq_item_export is by default present in ahb_msequencer
    //now we have the driver connected to the sequencer, and that they are connected
    //by sequence item port
endfunction:connect_phase
endclass: ahb_magent
Save the above as ahb_magent.svh

In the above code, it can be seen that 'pointers' or 'handle' to sequencer and driver are declared thus:
ahb_msequencer ahb_msequencer_h;
ahb_mdriver ahb_mdriver_h;
These components are then built using the following code inside the 'build_phase' function:
    ahb_msequencer_h = ahb_msequencer::type_id::create("ahb_msequencer_h",this);
    ahb_mdriver_h    = ahb_mdriver::type_id::create("ahb_mdriver_h",this);

Agent is the uvm component, where we write the code to make connection between
a Driver and a Sequencer, so that the transactions generated in a sequence running on a sequencer may actually
be piped to the driver.
An agent will usually use a function called 'connect_phase', and in this function we make the
explicit connection of the driver and the sequencer using the following code line:

ahb_mdriver_h.seq_item_port.connect(ahb_msequencer_h.seq_item_export );

Here we are making a connection between a predefined port called 'seq_item_port' present in the uvm base class uvm_driver
to the predefined port called 'seq_item_export' present in the uvm base class uvm_sequencer.

This completes this Agent Class Chapter.

<- Previous(Sequencer Class)                                                                           Next -> (Environment Class)

KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.