UVM Tutorial Env Class

OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal

Env (Environment) Class.
An env class is derived from the uvm base class 'uvm_env'.
The env class is the one which will have all the agents instantiated in it.

class ahb_env extends uvm_env;
`uvm_component_utils(ahb_env)

ahb_magent ahb_magent_h;
my_dut_config my_dut_config_env_0;

function new(string name , uvm_component parent);
    super.new(name,parent);
endfunction: new

function void build_phase(uvm_phase phase);
    ahb_magent_h = ahb_magent::type_id::create("ahb_magent_h",this);
    my_dut_config_env_0 = new();
    assert (uvm_config_db #(my_dut_config)::get(this,"","dut_config",my_dut_config_env_0));
    ahb_magent_h.dut_agent_vi = my_dut_config_env_0.dut_config_vi_0;
endfunction: build_phase
endclass: ahb_env

Save the above as ahb_env.svh

This completes this Env Class Chapter.

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.