UVM Tutorial Test Class

OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal

Test Class.
An test class is derived from the uvm base class 'uvm_test'.
By the UVM standard definition, the test class is the one which will have all the envs instantiated in it.
A test class is also the one which will actually run a test.
However, we would write a basic test class first, which wont actually run any test, it will only instantiate
the env class, and do some configuration settings.
More about configuration will be explained later.
Then we will write our actual test classes, which will correspond to 1 test on the DUT each, which will
be derived from this test class.

class ahb_test extends uvm_test;
`uvm_component_utils(ahb_test)
ahb_env ahb_env_h; //handle to env
my_dut_config my_dut_config_test_0;

function new(string name, uvm_component parent);
    super.new(name,parent);
endfunction: new

function void build_phase(uvm_phase phase);
    ahb_env_h = ahb_env::type_id::create("ahb_env_h",this);
    my_dut_config_test_0 = new();
    //get the virtual interface from the top module, and put it in config object my_dut_config_test_0.
    assert (uvm_config_db #(virtual ahb_if)::get(this,"","dut_vi_app_m0",my_dut_config_test_0.dut_config_vi_0));
    uvm_config_db #(my_dut_config)::set(this,"*","dut_config",my_dut_config_test_0);
endfunction: build_phase
endclass: ahb_test

Save the above as ahb_test.svh

This completes this Test Class Chapter.

<- Previous(Env Class)                                                                           Next -> (Top Test Class)

KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.