UVM Tutorial Top Test Class

OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal

Top Test Class.
Finally we define a Top Test class, which will instantiated the basic test class.
This top test class will be called 'test_all'. This will be derived from the test class
previously declared, i.e. from 'ahb_test'.
This is where we will write the code to run a UVM test.
This test name will be used with the VCS command line to tell the VCS simulation
executable, which test to run using the VCS option +UVM_TESTNAME

class test_all extends ahb_test;
   `uvm_component_utils(test_all)

     function new(string name, uvm_component parent);
        super.new(name, parent);
     endfunction: new
     logic enable_if01;

     int itr_01;

     task run_phase(uvm_phase phase);
        ahb_msequence seq;
        ahb_idleseq   idle_seq;
        all_addr_ranges ar_01;

        enable_if01 = 1;

        itr_01 = 150;

        fork begin
          if(enable_if01) begin
            repeat(itr_01) begin
              ar_01 = all_addr_ranges::type_id::create("ar_01");
              assert(ar_01.randomize());
              seq = ahb_msequence::type_id::create("seq");
              assert (seq.randomize());
              seq.haddr = ar_01.haddr_01;
              phase.raise_objection(this);
              seq.start(ahb_env_h.ahb_magent_h.ahb_msequencer_h);
              phase.drop_objection(this);
            end //repeat(itr_01)
            idle_seq = ahb_idleseq::type_id::create("idle_seq");
            idle_seq.randomize();
            idle_seq.start(ahb_env_h.ahb_magent_h.ahb_msequencer_h); //m_sequencer is a keyword
          end //if(enable_if01) begin
        end
        join
     endtask // run_phase
endclass: test_all

Save the above as ahb_test_all.svh

This completes this Top Test Class Chapter.

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.