OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal


Package Definition(s).
Before we start to compile the uvm code, let us try to organize the files in a package.
We will call this package ahb_pkg.

package ahb_pkg;
  `include "uvm_macros.svh"
  import uvm_pkg::*;
  `include "ahb_mtran.svh"
  `include "all_addr_ranges.svh"
  `include "ahb_msequencer.svh"
  `include "my_dut_config.svh"
  `include "ahb_mdriver.svh"
  `include "ahb_magent.svh"
  `include "ahb_env.svh"
endpackage: ahb_pkg


Save the above as ahb_pkg.sv

We also define some more packages such has
Sequence Package : To keep all sequences in an organized fashion.
Test Package : To keep all tests in an organized fashion.

Sequence Package:
package ahb_mseqs_pkg;
  import uvm_pkg::*;
  import ahb_pkg::*;
  `include "ahb_idleseq.svh"
  `include "ahb_msequence.svh"
endpackage
Save the above as ahb_mseqs.sv


Test Package:
package ahb_test_pkg;
  import uvm_pkg::*;
  import ahb_pkg::*;
  import ahb_mseqs_pkg::*;
  `include "ahb_test.svh"
  `include "ahb_test_all.svh"
endpackage

Save the above as ahb_pkg.sv



This completes this Package Definition(s) Chapter.

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.