UVM Tutorial Verilog Top Module

OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal

Verilog Top Module

In this module we will instantiate an interface which will be driven by the UVM TB.
The interface will then be mapped to the virtual interface the 'driver' is driving.
This module will also call UVM method 'run_test' which will enable us to run
various tests we would write using this UVM Verification environment.
The run_test() method call actually creates an instance of ahb_test class.

module top;
import uvm_pkg::*;
import ahb_pkg::*;
ahb_if ahb_if1 ();

dut dut1(._if1(ahb_if1));

initial begin
    ahb_if1.hclk = 0;
    forever #5 ahb_if1.hclk = ~ahb_if1.hclk;
end

initial begin
    ahb_if1.hresetn = 0;
    #11 ahb_if1.hresetn = 1;
end

initial
begin
    //the following is a command
    uvm_config_db #(virtual ahb_if)::set(null, "uvm_test_top","dut_vi_app_m0", ahb_if1);
    //             (type of value)      prefix path           name/value pair
    //the above is specifically done for "uvm_test_top", so only 'test' can
    //look for "dut_vi_app_m0".
    run_test(); //this will create an instance of ahb_test class
end

endmodule: top

This completes this Verilog Top Module Chapter

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.