OVM/UVM: A Practical Tutorial Using System Verilog

-Aviral Mittal


Synopsys Run Script
Following is the Synopsys VCS run script (run.scr).

vcs -debug_all -sverilog -override_timescale=1ps/1ps\
+incdir+/pkg/software/uvm/uvm-1.1d_r2/release/src\
+incdir+/pkg/software/uvm/uvm-1.1d_r2/release/src\
/pkg/software/uvm/uvm-1.1d_r2/release/src/dpi/uvm_dpi.cc\
/pkg/software/uvm/uvm-1.1d_r2/release/src/uvm_pkg.sv\
../source/ahb_intf.sv \
../source/ahb_pkg.sv \
../source/ahb_mseqs_pkg.sv \
../source/ahb_test_pkg.sv\
../source/ahb_slave.v \
../source/top.sv \
../source/dut.sv \
+incdir+/pkg/software/uvm/uvm-1.1d_r2/release/src \
+incdir+../source
./simv -quiet +UVM_TESTNAME=test_all -gui



This completes this Synopsys Run Script Chapter.

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.